The unit combines four existing divisions: netbooks and tablets, ultra mobility (smartphone processors), mobile communications (baseband) and mobile wireless (Wi-Fi).

The idea, it said, is to “speed up and improve the development process.”

At least there’ll be less duplicated effort, but what Intel needs and quickly is a winning energy-efficient design.

It’s supposed to have a new Atom mobile chip code named Medfield early next year. The widget and Intel’s alliance with Google to optimize Android for the Atom may or may not improve its traction (while its old buddy Microsoft cozies up to ARM and ports Windows 8 to its architecture).

The new group will be run two-in-box by Hermann Eul, once a top Infineon executive, and Mike Bell, who used to work at Apple on the iPhone and joined Intel last year from Palm.

Bell has co-managed the old ultra mobility unit since March and after Intel acquired Infineon and before his latest apotheosis, Eul was running Intel’s Mobile Communications Division, created out of Infineon.

Fortune broke the reorg story Wednesday morning when Intel sent out an internal memo and Intel confirmed it.

Earlier this week, Intel cut its Q4 guidance on reduced orders caused by the hard drive shortage created by the crippling floods in Thailand.

Tilera, the many-core general-purpose chip start-up, however, is promising some gladiatorial entertainment for those into blood sports.

It thinks it can kick Intel in the shorts and out of the cloud business with chips that with a little recompiling run the same Linux software as Intel but deliver 10x the performance-per-watt of an Intel Sandy Bridge.

Tilera’s director of cloud computing products and marketing Ihab Bishara says chip makers (read Intel) can’t get away with paltry 15%-20% improvements. They have to make orders-of-magnitude jumps.

Tilera figures it’s two years ahead of any wannabe ARM servers and a year ahead of Intel, which might be able to pull something together with its hydra-headed Larrabee chip, now Intel’s Many Integrated Core (MIC) architecture.

It’s pointing the thing at the Web 2.0 server market that’s growing at the rate of 20% CAGR versus the enterprise server’s measly 9%.

For the last two years Tilera has been in a huddle with what it says are “the world’s leading cloud companies,” names it dare not speak, but which obviously have to be, oh, Facebook, Google and Amazon.

And they have been “co-developing,” no less, the new TILE-Gx 3000 processor family that Tilera unveiled Tuesday.

It’s described as the “ultimate cloud computing processor” and is supposed give the cloud boys exactly what they want, slashing all-important power consumption and footprint 80%.

Each of the Gx 3000’s cores – and the dingus will be available with 36, 64 and 100 cores – consume less than 0.5 watts at 1.5GHz. The widgets are optimized for cloud data centers and are supposed to provide an estimated 50% reduction in total cost of ownership (TCO).

Aside from power consumption, the single biggest issue for cloud companies, Tilera is also meeting their 64-bit and error correction demands so it can hit the sweet spot of high performance and low power.

It says its cloud customers have already placed orders although the first version of the part, the 36-core, won’t sample until the end of July, followed by the 64-core and the company’s first 100-core in Q1 next year.

Tilera says the device is targeting scale-out data centers running throughput-oriented applications including:

• Web applications that need high-throughput processing and low latency.

• Database applications like NoSQL and in-memory databases that require high-memory throughput and storage.

• Data mining applications like Hadoop that rely on high disk throughput and data processing.

• And video transcoding that necessitates throughput processing.

The 36-core TILEGx-3036 is supposed to replace single-socket servers; the 64-core 3064 will replace dual-socket servers; and the 100-core 3100 will replace up to quad-socket servers.

They’re all built on Taiwan Semiconductor’s 40nm process. Each core features a three-issue, 64-bit ALU with an advanced virtual memory system. And each core includes 32 kilobytes (kB) of L1 I-cache, 32kB of L1 D-cache and 256kB L2 cache, with up to 32MB of L3 coherent cache across the device.

Part Number Core
Count Cache DDR3 PCIe 2.0 Controllers Ethernet Ports Power Availability
Gx3036 36 12MB Dual channels 1 x8 port
1 x4 port 2 x 1 Gb
2 x 10 Gb 20W Q3 2011
Gx3064 64 20MB Quad channels 2 x8 port
1 x4 port 2 x 1 Gb
2 x 10 Gb 35W Q1 2012
Gx3100 100 32MB Quad channels 2 x8 port
1 x4 port 2 x 1 Gb
2 x 10 Gb 48W Q1 2012

Processor utilization is optimized using advanced memory stripping that utilizes up to four integrated 72-bit DDR3 memory controllers supporting up to 1TB total capacity. The Gx 3000 family integrates smart NIC hardware for preprocessing, load balancing and buffer management of incoming traffic.

The widgets support a standard software stack like a Centos-compatible 2.6.36 Linux that supports 2,000-odd standard RPM packages; standard tools like Gcc, g++, gdb, gprof, oprofile, perf event, mudflap and eclipse; standard languages like ANSI C/C++, Java, PHP, Perl and Python; programming frameworks like Erlang, TBB and open MP; and standard management protocols like IPMI 2.0, SNMP, Syslog, Telnet, SSH, TFTP, FTP and SCP.

Tilera derived the Gx 3000 series by stripping out stuff like the networking I/O in the networking-oriented Gx 8000 architecture on which the processors are based.

Tilera’s 3000 samples will be available in the company’s own boxes. Third-party boxes – cloud people reportedly prefer cost-conscious ODM gear – should be available in the fall with production servers by the end of the year. Last time through the production boxes came from Quanta.

Tilera expects to be cash flow positive by the end of the year and wants to IPO by the end of next year, sooner than it said a couple of months ago. It recently raised a $45 million round. Total investment comes to $109 million including strategic investments from Cisco and Samsung.

It said the breakthrough, which basically puts a fin-like second story on the humble transistor, promises power reduction and performance improvement in everything from the smallest handheld to the biggest cloud-based servers.

Intel is going to use the newfangled 3D transistors, dubbed Tri-Gate after the fin’s three current-controlling gates, in making its 22nm Ivy Bridge chip, a Sandy Bridge shrink due out by the end of this year. It will also use them in its tablet- and phone-hopeful Atom chip, presumably giving it something to take up against ARM.

Because of the vertical enhancement Ivy Bridge will mean a 37% performance improvement at lower voltages than Intel’s 32nm planar models and consume less than half the power at the same performance as current Intel chips.

Intel first described the widgetry in 2002. It explained the other day at a demo that the new Tri-Gate transistors represent a fundamental departure from the usual 2D planar transistors and claimed the development will translate into “world-shaping devices” that “advance Moore’s Law into new realms.”

The wiring is so “incredibly thin,” Intel said, that more than six million 22nm Tri-Gate transistors can fit in the period at the end of this sentence.

Tri-Gate transistors should turn out chips that operate at a lower voltage with less leakage, giving developers a choice of transistors for low power or high performance depending on the application.

It’s already got new single-socket 20W 2.2GHz E3-1220L and 45W 2,4 GHz E3-1260L Xeons in production, with a 15W Sandy Bridge promised in the second half that are supposed to scratch the itch ARM may have tickled. There’s also a sub-10W Atom server chip due next year.

Everything coming will be 64-bit, with Intel Virtualization Technology built in and support ECC memory. Needless to say, it will be software-compatible.

Intel figures the micro servers they and their descendents will be based on could take less than a 10% slice of the overall server market in the next four-five years.

Facebook labs director Gio Coglitore, who admits to testing some of the early widgetry – presumably SeaMicro’s Atom servers, say, or Dell or Tyan Xeon jobs – seems to prefer such things to virtualizing more powerful infrastructure and imagines massively deploying micro servers later this year or next as front-end web servers. Losing a micro server has no impact on the user experience, he says, and requires no replacement.

Google, on the other hand, seems to prefer what it calls “brawny cores” to “wimpy cores” for throughput and parallelism whereas the “cost numbers used by wimpy-core evangelists always exclude software development costs.” There’s also the “wimpy” possibility of higher DRAM costs and lower utilization.

Intel first debuted the small, low-power, single-processor micro server concept in 2009 targeting the form factor at very dense installations. Next quarter it expects to have a new Micro Server Evaluation Lab set up where developers can analyze their software.

By comparison UBS 3.0 tops out at 5 Gb/s and the more common UBS 2.0 can only do 480 Mbps.

As widely bruited, Apple is its earliest adopter, sporting a Thunderbolt port complete with a lightning icon on its new MacBook Pros, where it will do double duty supporting both high-speed I/O and high-definition Mini DisplayPort devices on a single cable.

Apple is believed to have kicked in some know-how about mixing data and display.

The widgetry, which can run multiple protocols simultaneously over a single wire, is supposed to be capable of downloading a full-length high-def 10GB-20GB movie in 30 seconds. Such a feat would require fast disks and most likely implies a boxful of external drives.

Chip groupie Nathan Brookwood called it “an extremely clever approach for out-of-the-box expansion for desktop and notebook computers,” something that doesn’t exist for laptops right now like external graphics cards.

Intel, who will license the IP royalty-free to OEMs, promises speeds will eventually hit 100 Gbps.

The PCI Express side of the Thunderbolt equation is supposed to connect to almost any type of device – multiple ones daisy-chained together with electrical or optical cables – and Intel said the DisplayPort can drive screens with better than 1080p resolution and up to eight audio channels simultaneously.

Among other things Intel imagines faster backups and restores, thinner form factors, more flexible systems designs, cable simplification and spiffier media creation and connectivity.

The mojo, which also works with USB, FireWire and gigabit Ethernet, involves an Intel controller chip and a small display connector suitable for mobile devices.

Intel said it would be supported by Aja, Apogee, Avid, Blackmagic, LaCie, Promise and Western Digital and it figures it will appear in computers, displays, storage devices, cameras, audio/visual devices and docking stations.

The updated MacBooks, which start at $1,199, run on faster new Intel processors and new AMD Radeon graphics chips.

It is Intel’s biggest acquisition ever by a factor of three.

CEO Paul Otellini said during a conference call Thursday morning that the purchase “transitions Intel from a PC company to a computing company.”

Intel explained that that the acquisition, part of its mobile wireless strategy, will let it combine security software and hardware as billions of still relatively innocent, unprotected devices – and the server and cloud networks that manage them – go online. It also differentiates Intel from its competition.

The move is supposed to put security “on a par with energy-efficient performance and connectivity” as a pillar of its business. Intel’s vision includes TVs, cars, medical devices and ATM machines and it noted that cyber threats are spiraling out of control.

So a “fundamentally new approach” is needed and it promised that hardware-enhanced security would lead to breakthroughs in countering the increasingly sophisticated threats.

The move was immediately seen as a reach for inorganic growth with better margins in a business that’s less bumpy than chips. For instance, PC order trends have sharply deteriorated lately. McAfee does close to $2 billion a year, has seen 20% growth recently and fetched close to an 80% gross margin last year. It only makes about $200 million however.

The deal will cost Intel $48 a share in cash. Net of McAfee’s cash, it will cost Intel about $6.8 billion.

Intel will run McAfee as an independent subsidiary reporting to Intel’s Software and Services Group under Renée James.

The security house has 6,100 people. Intel says it will keep most of them including management. Aside from its antivirus widgetry, McAfee’s wares include end-point and networking products and services and an expanding line of gear targeting mobile devices such as smartphones, a market that’s been eluding Intel.

McAfee claims 200 million users.

McAfee has been frequently cited as acquisition bait but never in association with Intel. Intel said that a quiet partnership with McAfee over the last 18 months persuaded it to make the move and then it found a lot of other projects needed to be secured.

Otellini explained that it’s not a matter of bungling but of integration. He said Intel would still work with other security vendors.

The first combined McAfee-Intel products are due in the first part of 2011. James indicated they would involve Intel’s existing Core chips with Atom to follow. Deeper integration will take a while.

Intel means to keep the McAfee brand and to have it continue to support multiple platforms.

The acquisition is expected to dilute Intel’s GAAP earnings slightly the first year and be flat the second year.

The acquisition, already approved by both boards, will hopefully close by December.

Last year Intel bought the embedded OS Wind River.

It says the widget, the first of a family of Knights, will create HPC platforms running at trillions of calculations a second without sacrificing the benefits of standard x86 processors, a hard-won lesson learned from its Itanium adventure.

It means to create supercomputers that run most of their workloads on Xeon chips but accelerate specific highly parallel applications complements of the MIC architecture.

The anticipated 500 gigaflops systems will be aimed at uses such as exploration, scientific research and financial simulation.

According to none other than DreamWorks Animation CEO Jeffrey Katzenberg speaking at the chatty D8 conference the other day, Intel also has workstation intentions for the thing and the reason he called the thing Larrabee despite the fact that Intel canceled the prospective GPU last week is because the thing is Larrabee redirected.

In the initial 32nm developer prototype version that’s floating around out there Knights is a 32-core Larrabee. The first commercial product will be 22nm 50-core device that derives not only from the canceled Larrabee but also from the research-y ultra-low-power 48-core Single-Chip Cloud Computer that Intel disclosed in December and TeraScale.

Larrabee, as Intel puts it, will “use Moore’s Law to scale to more than 50 processing cores on a single chip.” Each of the cores will reportedly run at 1.2GHz, have 8MB of shared coherent cache and four threads apiece for a total of 128 threads. It’ll also support 1GB-2GB of GDDR5 memory.

The company’s already got design and development kits codenamed Knights Ferry shipping to hand-picked developers, and beginning in the second half it means to start delivering MIC developer tools. The trick is that they will share a lot of in common with Xeon tools as well as common software algorithms and programming techniques. The same languages, compilers and libraries can be used. It eliminates the need for a dual-programming architecture.

Apparently the CERN openlab team was able to migrate a complex C++ parallel benchmark to the MIC software development platform in just a few days. Its CTO Sverre Jarp said that “the familiar hardware programming model allowed us to get the software running much faster than expected.”

Since the dingus is 22nm it can’t go commercial until next year.

In Intel’s case it’s the two-billion-transistor Itanium 9300, a k a Tukwila, the device once known as Tanglewood, only about, oh, say, three years late – the thing has been redefined, renamed, tweaked and diddled so many times it’s hard to tell anymore – figure it’s somewhere between two and four years past due. Anyway, two billion transistors is Intel’s personal best and Tukwila quietly started shipping for revenue last month.

In IBM’s case it’s the Power7, out a couple of months sooner than expected, bound for boxes that Blue can use to ward off a Sun-armed Oracle as well as a redirected Cisco and old rival HP.

Tukwila promises to double the performance of its Montecito predecessor.

IBM, on the other hand, has managed an 8x jump over the Power6, and chip-for-chip is more powerful than Intel’s hard-won widget.

Chip groupie Nathan Brookwood describes Tukwila as the “first major overhaul of Itanium since McKinley in 2001″ and says that compared to Sun’s ill-fated Rock chip “it’s better late than never.”

Brookwood also says that IBM isn’t given enough credit for delivering Power upgrades in predictable tick-tock fashion, something it’s been doing since 2001, way before Intel coined the phrase.

The 3.5GHz-4GHz Power7 has eight cores – and four threads per core – four times as many cores and eight times as many threads per core as the 5GHz Power6. Tukwila is only a two-threads-per-core quad replacement for the dual-core Montecito while IBM will be able to replace four Power6 chips with one Power7, which should mean a significant cost savings.

If Intel replaces two Montecitos with one Tukwila, Brookwood says “it’s still just breaking even on cores.” At the same 2:1 ratio IBM would be up four cores.

One thing Power can’t do is run Windows and stuff like SQL Server. Itanium can and since Xeon is inching up on Itanium’s RAS skills because of increasingly common platform ingredients, it’s possible that with this generation some of Itanium’s hangers-on could bolt to the eight-core 16-thread Tukwila-socket-compatible Nehalem EX when it arrives.

Anyway, Tukwila has eight threads per processor complements of enhanced Intel Hyper-Threading; uses QuickPath Interconnect technology, Intel’s version of AMD’s HyperTransport technology so there’s no front-side bus; 30MB of cache; is endowed with Turbo Boost Technology to automatically rev performance when needed and conserve power when it’s not based on workload; and – according to the chip’s press agents – has up to 800% the interconnect bandwidth, 500% the memory bandwidth and 700% the memory capacity using industry-standard DDR3 components than Itanium used to have.

Oh, yes, and there’s second-generation Intel Virtualization Technology in the thing; the Intel 7500 chipset can directly assign I/O devices to virtual machines.

Intel Monday announced two new OEMs – well, one out-of-blue, the other merely confirmed. Supermicro, the channel OEM, whose interest was established, is gonna start selling four-socket Tukwila machines.

The surprise is Inspur, a Chinese company evidently with global ambitions that Intel says the Chinese government picked to deliver Itanium solutions. Itanium is gonna be losing Red Hat support although RHEL 5 is good through 2014. Of course, HP represents 85% of Itanium sales and said it would have Tukwila systems out in 90 days.

Between now and 2014 Intel should conceivably field two more versions of Itanium: Poulson, an already late 32nm, 45nm-skipping shrink of the 65nm Tukwila, due maybe who knows in a couple of years, and Kittson about which next to nothing is known except that it should be socket- and binary-compatible with Tukwila and Poulson.

Poulson, Intel said, will have more parallelism, more cores, more cache, Hyper-Threading improvements and instruction-level enhancements compared to Tukwila.

Until then the Itanium 9300 ranges in price from $946 to $3,838 in quantities of 1,000.

Intel would probably like us to repeat that Itanium managed to claw out a $5 billion-a-year systems business in 2008 that probably dropped to $4 billion last year because of the recession but that its RISC rivals, such as they are, are dropping too, probably from $22 billion in ’08 to $16 billion.

Now about the Power7 and remember that IBM is still the Unix winner with roughly 40% of the market.

Since Oracle is aiming its Sun boxes directly at Blue, IBM said its new Power 750 Express delivers 71% better price/performance than a Sparc Enterprise T5440 server and 280% better price/performance than Sparc Enterprise M5000 and M4000 servers. It’s also supposed to deliver more than 400% better price/performance than the existing HP Integrity rx7640 or the rx6600 servers.

IBM is gonna put out four new Power systems: the Power 780 and Power 770 each with up to 64 Power7 cores, the latter consuming up to 70% less energy for the same number of cores as the Power 570; the Power 755, a high-performance computing cluster node with 32 Power7 cores optimized for analytic workloads; the Power 750 Express, an Energy Star-qualified business server for the mid-market offering four times the processing capacity of its predecessor; and the Power 550 Express in the same energy envelope at a reported 10x the performance of a comparable HP Integrity rx6600.

The Power 750 is supposed to be three times more energy-efficient than the Sparc Enterprise T5440, Sun’s so-called Coolthreads server.

Naturally, the gismos support the advanced virtualization management capabilities of VMControl, which manages a systems pool of multiple Power servers as one entity, which should cut management costs.

The Power 750 Express and 755 should ship February 19; the 770 and 780 should start going out March 16. Planned availability for Systems Director Editions supporting both Power7 and Power6 models – as well as mainframes and x86 boxes – is March 5.

IBM says it’s “vastly increased” the parallel processing capabilities of Power7 systems optimized for databases and delivered a “leap” in throughput computing optimized for running massive Internet workloads.

It also says it’s “dramatically increased” the parallel processing capabilities of its WebSphere, DB2, InfoSphere Warehouse and Cognos middleware for managing Internet, data, transactions and analytics to support Power7 systems. The software will be able to exploit all 32 threads available in a single eight-core Power7, reportedly resulting in performance gains over Intel’s Nehalem chip.

The Power7′s TurboCore mode, which is optimized for database and other transaction-oriented workloads, runs with four cores active and puts most of the resources from all eight cores on the chip behind just the four active cores giving them more cache memory and memory bandwidth, so the clock speed can be increased, driving per-core performance gains.

IBM says its TurboCore mode can maximize the ROI from software by potentially reducing software costs in half for applications licensed per core, while increasing per-core performance.

When not in TurboCore mode, Power7 processors run in so-called MaxCore mode with up to eight cores per socket and four threads per core – 32 threads total. Power7 has so-called Intelligent Threads that can dynamically vary based on workload demand, increasing capacity and total performance gains.

For workloads that need large amounts of memory, or in virtualized environments where more memory is beneficial, clients can use a new Power7 technology called Active Memory Expansion that uses memory compression technology to make the physical memory on the system look to applications as though it was up to twice as big as it actually is, transparently compressing more data into memory and expanding the memory capacity of Power7 systems.

IBM estimates up to a 65% increase in transactions or users could be handled by the same server previously constrained by memory capacity.

The chip, Intel’s first standalone discrete graphics chip and a test of its multi-core prowess, was already late, and hardware and software development had fallen behind schedule.

Intel swears it’s “absolutely committed” to the idea but with a different chip.

Larrabee was based on the x86 architecture to make it easier to program and reportedly could have had as many as 32 cores. Intel never was definite about that.

Embarrassed by its failure, Intel’s decided to say nothing about its next step until it knows exactly what it is and has confidence it’s on track. Mind you, it’s been talking up Larrabee since early 2007.

Meanwhile, to salve its bruised ego, the company points out that the new Arrandale and Clarkdale Core processors due out early next year will integrate graphics into the CPU, but admits it’s not the whiz-bang high-end graphics of the might-have-been Larrabee effort, although Larrabee’s performance supposedly left analysts unimpressed when demoed at IDF in September.

Since the Larrabee had a heartbeat it will be used as a beta or SDK, an Intel spokesman said.

Intel will now have to concede the immediate future to AMD’s Evergreen and Nvidia’s prospective Fermi GPUs and pick a new battleground. AMD’s first Fusion (GPU + CPU) products aren’t expected until 2011.

Microsoft, ETH Zurich, the University of California at Berkeley and the University of Illinois already have one and researchers from Intel, HP and Yahoo’s Open Cirrus initiative have already begun porting cloud applications to the widget using Hadoop, the Java software framework that supports data-intensive distributed applications.

Internally Intel has ported web servers, physics modeling and financial analytics to the thing.

Intel says SCC, which runs Windows and Linux and so legacy software, is a research platform meant to work out the many kinks of multi-headed programming. It will never be a product.

However, Intel means to start integrating key features of the work in a new line of Core-branded chips early next year and introduce six- and eight-core processors later in 2010.

The SCC dingus – the most x86 engines ever pushed onto a single sliver of silicon – only consumes 25W-125W with all its little cores chugging away at maximum performance.

That’s the equivalent of a couple of light bulbs – or a Nehalem chip – thanks to newly invented fine-grain power management techniques and Intel believes it could reshape how computers are built and how people interact with their PCs and personal devices.

SCC incorporates technologies such as the power management and scale-out message-passing intended to scale to 100 cores and beyond but before such a device can go mainstream Intel’s got to understand better how to schedule and coordinate many cores.

Once that problem’s linked it believes laptops will be able to see objects and motion as it happens the same way a human being does and with a high degree of accuracy.

It says to imagine a world without keyboards, remote controls or joysticks because computers may be able to read brain waves, so simply thinking about a command, such as dictating words, would happen without speaking.

Or, if you figure you’ll be dead before that happens, imagine shopping online and seeing a “mirror” of yourself wearing the clothes you’re interested in and twirling to see how the fabric drapes and checking if the color complements your skin tone.

Very Jules Verne and gee-whiz but not any problem Intel is immediately trying to solve. It’s really trying to squeeze a container-based data center Cinderella-style into a rack.

Intel says it calls the futuristic chip a Single-Chip Cloud Computer because architecturally it resembles the organization of data centers used to create a cloud of computing resources over the Internet.

That means tens to thousands of computers connected by a physically cabled network, distributing large tasks and massive datasets in parallel. The chip uses the same approach, but all the computers and networks are integrated on a single piece of 45nm, high-k metal-gate silicon about the size of a postage stamp, dramatically reducing the amount of physical computers needed to create a cloud data center.

There’s a high-speed 256 GB/s network between the cores in the chip that Intel says significantly improves the communications performance and energy efficiency of the current data center model, since data packets only have to move a few millimeters on-chip instead of tens of meters to another computer system.

Applications will be able to use this low-latency mesh network to pass information directly between cooperating cores in microseconds, reducing the need to access data in slower off-chip system memory. Applications can also dynamically manage exactly which cores are used for a given task at a given time.

Each of the cores can run an operating system and Intel says software can turn each of the cores off and on and match their voltage and clock speed levels to the needs of the moment. Each dual core or tile can have its own frequency and groups of four tiles or eight cores can run at their own voltage.

In a canned quote, Dan Reed, Microsoft’s corporate VP of extreme computing, remarked that “Our early research with the single chip cloud computer prototype has already identified many opportunities in intelligent resource management, system software design, programming models and tools, and future application scenarios.”

David Andersen, assistant professor of computer science at Carnegie Mellon, figures “the chip’s massive parallelism gives us the ability to investigate, today, the degree of parallelism that will be needed from applications five years down the line to make the best use of emerging many-core platforms.”

The prototype, an x86 follow-on to the 80-core non-x86 Polaris chip Intel unveiled two years ago, was developed by Intel Labs in Bangalore, India, Braunschweig, Germany and Hillsboro, Oregon as part of the company’s Tera-scale Computing Research Program.

Intel says it will detail the widget’s 24 dual-core or tile architecture and circuits in a paper to be presented at the International Solid State Circuits Conference in February.

Apparently the 1.3 billion-transistor concept chip, as Intel calls it, shares some attributes with Intel’s upcoming Larrabee GPU microarchitecture but not its cache-coherent design.

Tilera has a 100-core chip that it expects to put out next year.